As the semiconductor devices keeps scaling down in size, three-dimensional multi-gate structures, such as the fin-type field effect transistor (FinFET), have been developed to replace planar Complementary Metal Oxide Semiconductor (CMOS) devices. A structural feature of the FinFET is the silicon-based fin that extends upright from the surface of the substrate, and the gate wrapping around the conducting channel that is formed by the semiconductor fin further provides a better electrical control over the channel.
During fabrication of FinFETs, the semiconductor fins are patterned by fin cut last process to remove unwanted portions of the semiconductor fins, and after the fin cut process, shallow trench isolations (STI) and gate stacks are then formed. During the fin cut process, a patterned photoresist layer is forming to partially cover the semiconductor fins and the unwanted portions of the semiconductor fins are etched. Since the patterned photoresist layer used in fin cut process is formed over the substrate and may not be sufficient thick to protect the semiconductor fins covered thereby, especially the semiconductor fins distributed in a dense area (e.g., core area) of an integrated circuit. Thus, fin damage occurs during the fin cut process and stability of the fin cut process deteriorates.